1. Field of the Invention
The present invention relates to a semiconductor device with trenches having larger and smaller opening widths at a surface of a semiconductor substrate respectively.
2. Description of the Related Art
Non-volatile memories such as flash memories include a memory cell region in which a number of cell transistors are formed and a peripheral circuit region which is formed to drive the cell transistors and transistors of high breakdown voltage type are provided. The peripheral circuit region necessitates a longer insulation distance than the memory cell region since the transistors have higher breakdown voltages than the cell transistors. These elements are provided in an active region of the semiconductor substrate separated by a shallow trench isolation (STI) structure.
With recent refinement of design rules, a trench width of STI has been reduced such that an aspect ratio (a ratio between the width and the height of the trench) tends to become higher. It has technically been difficult to form STI with a high aspect ratio because of etching accuracy and the trench fill capability of an insulating film. In view of the aforementioned problem, a trench which is as shallow as possible is formed in the memory cell region so that the trench opening is narrowed since the cell transistors do not require high breakdown voltage, and regarding the transistors in the peripheral circuit region which require high breakdown voltage, the trench opening is widened since the trench needs to be rendered deeper for the purpose of securement of the breakdown voltage. As a result, the aspect ratio is prevented from being increased.
Accordingly, STI trenches of the memory cell and peripheral circuit regions need to have depths different from each other. In an actual trench forming step (hereinafter referred to as “a first conventional method”), an etching process is carried out in two steps. More specifically, a first silicon oxide film, a first polycrystalline silicon film, a silicon nitride film and a second silicon oxide film are sequentially deposited on a silicon substrate. Subsequently, a photoresist is formed by the photolithography process into a predetermined pattern. The second silicon oxide film and silicon nitride film are etched by a reactive ion etching (RIE) process with the photoresist serving as a mask. After the photoresist has been removed, the second polycrystalline silicon film, first silicon oxide film and silicon substrate are etched with the second silicon oxide film serving as a mask. In this case, a trench having a uniform depth is formed in the silicon substrate.
In order that a part of the trench at the peripheral circuit region side may be rendered deeper, a photoresist is patterned on a part corresponding to the memory cell region by the photolithography. The trench in the peripheral circuit region is etched with the photoresist serving as a mask until a predetermined depth is obtained, whereupon the trench has different depths in the peripheral circuit region and the memory cell region. Thus, since the depths of the trench differ in the memory cell and peripheral circuit regions, the STI width in the memory cell region can be reduced to a minimum according to the aspect ratio, whereas the depth according to the breakdown voltage can be ensured in the peripheral circuit region.
JP-A-2000-156402 discloses another method of forming a trench having different levels of the bottom (hereinafter referred to as “a second conventional method”). Trenches having a larger opening width and a smaller opening width respectively are formed in the semiconductor substrate. The trench with the larger opening width has a bottom including a central part higher than the other part of the bottom.
The second conventional method has an advantage that each of the photolithography and etching processes needs to be carried out only once. However, this method cannot provide a shallower trench with a smaller opening width and a deeper trench with a larger opening width. More specifically, one trench with the smaller opening width needs to be shallower and another trench with the larger opening width needs to be deeper. In the above-described fabricating method, the level of the central region of the trench with the larger opening width is increased while both trenches have the same depth. Thus, this method cannot be employed because a trench made by this method has a reverse condition.
The trenches of the memory cell and peripheral circuit regions cannot be formed simultaneously in the first conventional method. Each of the photolithography process and etching process needs to be carried out at least twice. As a result, since the number of fabrication steps in the forming of trenches cannot be reduced, the production yield cannot be improved and the production cost cannot be reduced.